DMS Verification Engineer (Electrical Engineer Post) Job Notification Location-California, United State

Front Office Associates Executives Job

DMS Verification Engineer Job | www.eduempworld.com |

DMS Verification Engineer Job | The DMS Verification team is searching for a self-motivating, passionate electrical engineer for the role of DMS Verification Engineer. As a member of the DMS team, Apple is looking for a strong candidate who can take on diverse challenges in verifying digital/mixed-signal designs in wireless radio transceivers.

Job Summary

Name of post – Electrical Engineer.

Work Schedule – Full-Time – full-time.

Location – Santa Clara Valley, California, United States.

Experience – least 8 years of experience.

Knowledge – Knowledge of UVM-AMS is a plus.

Education – MSEE with 5 years of analog verification experience or analog design experience with behavioral modeling.

Additional Requirements – Apple is an Equal Employment Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities.

Other Key Qualifications – 

  • Experience in analog behavior modeling and analog mixed-signal simulations.
  • Familiarity with System Verilog, System Verilog testbenches, sv-2012 Real, wreal.
  • Hands-on experience with Analog Assertion-Based Verification.
  • Design background to analyze verification results.
  • Experience writing scripts in languages such as Perl or Python.
  • Understanding of analog/mixed-signal blocks like PLL, ADC, DAC.
  • Excellent teammate with excellent communication skills

Description – 

What will you do in this role?
As a DMS Verification Engineer, you will be responsible for performing the verification of digital/mixed-signal designs including :
-Development of analog behavior models in Verilog or System Verilog
– Verifying analog functions – for example, coding test scenarios and environments for analog verification and/or

the assertion
– Working multi-functionally with Analog Designers setting up AMS simulation environment.
– Supporting mixed-signal co-simulation using Verilog models of analog IP

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